1. Field of the Invention
The invention relates to communication of data between a transmitter and a receiver. It is particularly applicable to communication systems where the data is transmitted over a time-variant or frequency-variant channel, such as in mobile communication systems or satellite communication.
2. Description of the Related Art
This invention addresses the bit to symbol mapping for higher order modulation schemes and rate matching, e.g. in a system employing link adaptation by Adaptive Modulation and Coding (AMC) as described for example in 3GPP TS 25.308; “High Speed Downlink Packet Access (HSDPA); Overall description; Stage 2”, v. 5.3.0, December 2002 and in A. Burr, “Modulation and Coding for Wireless Communications”, Pearson Education, Prentice Hall, ISBN 0 201 39857 5, 2001. AMC is used e.g. in 3GPP HSDPA, see for example in 3GPP TS 25.308, cited above, and 3GPP TS 25.212; “Multiplexing and Channel Coding (FDD)”, v. 5.3.0, December 2002.
In higher order modulation schemes, a plurality of bits b1, . . . , bi, . . . , bn (generally n>2) is mapped onto one symbol. This plurality of bits can be expressed as a binary word (or vector of bits) b1 . . . bi . . . bn, wherein to each value of this word or vector a certain modulation state is assigned. This assignment is called the “mapping” of bits to symbols. The order number i specifies the position of a certain bit (digit) within this word or vector and is hence called the “bit position”.
Due to noise and different kinds of distortion in the transmission chain (channel), there is a certain probability for defined values of the bits b1 to bi−1 and bi+1 to bn, that the transmission chain (channel) will erroneously alter a value “0” of bit bi, input into the mapper and modulator, into a value “1”, output from the demodulator. Accordingly there is a probability for turning a “1” into a “0”, which may be equal to the first probability. Averaging these probabilities for “0” and “1” and for all combinations of values of the other bits yields an error probability for bit bi regarding to the transmission chain.
Further herein below, the term “high reliability” related to a bit position will be regarded as equivalent to “low error probability” and the term “low reliability” related to a bit position will be regarded as equivalent to “high error probability”. In most cases reliability may me regarded upon as inversely proportional to the error probability. For a detailed discussion of reliability and error probability of bit positions in modulation schemes see Ch. Wengerter, A. Golitschek Edler von Elbwart, E. Seidel, G. Velev, M. P. Schmitt, “Advanced hybrid ARQ technique employing a signal constellation rearrangement,” IEEE VTC 2002 Fall, vol. 4, pp. 2002-2006, 2002.
Depending on the modulation scheme and on the applied mapping of words to symbols, different bit positions may possess similar or equal error probabilities or significantly different error probabilities.
FIG. 1 shows a simplified typical Physical Layer (PHY) transmitter processing chain, when AMC is applied. K information bits including CRC bits are fed into a channel encoder 101 (e.g. Turbo coding, convolutional coding, LDPC coding, etc.), which encodes the information bit sequence typically block wise into a N bit sequence (typically N>K). The encoder type and rate may be fixed or may be controlled by the AMC control unit 102. The encoder generates a sequence of “original” bits encoded at rate rEC=K/N. The output of the encoder is fed into a rate matching block 103, which outputs L “transmission” bits. This adjusts the encoder rate rEC according to the AMC control 102 (e.g. based on channel estimation) to rRM=K/L. The rate matching typically implements puncturing and repetition, i.e. if L<N, bits are punctured and if L>N, bits are repeated. However, puncturing and repetition may also be applied simultaneously, i.e. some bits may be punctured and some bits may be repeated. In this case, for L<N the puncturing rate is greater than the repetition rate and for L>N the puncturing rate is smaller than the repetition rate.
It should be noted that in the context of the description below, repetition for the purpose of rate matching is regarded, as opposed to ARQ (Automatic Repeat reQuest), where the repetition is based on information on the quality of the received data, fed back by the receiver via a transmission channel in the opposite direction. That is, the repetition regarded herein is taking place within the same transmission attempt as the original transmission, in most cases even within the same data block.
Furthermore it can be assumed that bits are not punctured and repeated at the same time, that is, punctured bits are not transmitted at all and therefore also not repeated.
The output of the rate matching 103 is then usually interleaved, where the used interleaver type or the interleaver parameters may also be controlled by the AMC control unit. The output of the interleaver 104 is then fed into the modulator (mapper) 105, which maps the bits onto modulation symbols. The modulation scheme is controlled by the AMC control, i.e. the selected M-ary modulation scheme (e.g. QPSK, 8 PSK, 16 QAM, 64-QAM) generates L/M modulation symbols according to the defined mapping and signal constellation.
In the following, the prior art is described with respect to current 3GPP HSDPA PHY processing chain implementation as shown in FIG. 2 (from 3GPP TS 25.212, cited above). For the sake of simplicity only relevant blocks are shown. The stream of original bits output from HSDPA rate 1/3 Turbo encoder 201 is fed into the rate matching block 203 by three bit streams (systematic bits, parity 1 bits and parity 2 bits). The rate-matching adapts the code rate according to an AMC control unit, which defines the number of output transmission bits to be generated by the rate matching. The rate-matching block 203 performs puncturing and/or repetition of its input bits according to the rate matching algorithm specified in 3GPP TS 25.212. Note that the rate matching in HSDPA is performed in two steps in order to allow practical hybrid ARQ (Automatic Repeat reQuest) operation, see FIG. 17 in 3GPP TS 25.212. In the bit collection block 206, the three output streams of the rate matching block are written into a matrix with either Nrow=4 rows (for 16 QAM) or Nrow=2 rows (for QPSK) and an according number of columns. The following description will focus on the operation with 16 QAM. The matrix is written such that the first rows are filled preferably with systematic bits and the remaining space is filled alternating with parity 1 and parity 2 bits (details can be found in section 4.5.4.4 in 3GPP TS 25.212) as shown for different rates rRM in FIG. 3 and FIG. 4. Note that the shown puncturing patterns, repetition patterns and block sizes may not exactly match the HSDPA specification, but are used in order to illustrate the general concept. Then the transmission bits from rows 1&2 and rows 3&4 are separately interleaved in interleavers 204a and 204b and fed into the modulator 205. The transmission bits from Interleaver 1 (204a) are mapped onto the bit positions i1 and q1 and the transmission bits from Interleaver 2 (204b) are mapped onto the bit positions i2 and q2 of the 16 QAM signal constellation. (see FIG. 5 for a mapping example with i1 and q1 mapped on high reliable positions and i2 and q2 mapped on low reliable positions).
The explained HSDPA implementation assures that preferably the systematic bits are mapped onto the bits i1 and q1. Assuming that a 16 QAM mapping as shown in FIG. 5 is used, this assures that transmission bits of the systematic original bits are mapped onto the 16 QAM high reliable positions.
US 2003/0120995 A1 is related to the SMP (Symbol Mapping method based on Priority) technique, which has been adopted for 3GPP HSDPA (as described above). SMP splits the bit sequence into two bit streams with different priorities. The high priority bit stream is mapped onto the M-QAM (or M-PSK) high reliable positions and the low priority bit stream is mapped onto the low reliable positions. The priority of a bit is dependent on the contents of a bit, i.e. whether it is a systematic bit (high priority) or a parity bit (low priority). Bits are written row wise into a matrix (buffer) and read column-wise.
Prior art does not consider the variations in bit reliabilities when mapping repeated bits onto higher order modulation schemes, i.e. when a bit is repeatedly transmitted (that is, several transmission bits of the same original bit are transmitted), its reliability increases with respect to non-repeatedly transmitted bits. E.g. according to the HSDPA implementation as shown in FIG. 2, for the 16 QAM (rRM=0.25) example the repeated bits are mapped (randomly) on any 16 QAM bit position (see repeated bits with hatched background in FIG. 4). Here, whether a bit is (preferably) mapped onto a high reliable position (i1 and q1) or on a low reliable position (i2 and q2) depends on its content, i.e. depends on whether a bit is a systematic bit or a parity bit.
The prior art schemes cause disadvantages in decoding, since after soft combining of the repeated bits, the bit reliabilities (of all bits) show significant variation.